The performance of many digital systems is limited by the interconnection bandwidth within and between integrated circuit devices (ICs). High performance communication channels between ICs suffer from many effects that degrade signals. Primary among them are frequency dependent channel loss (dispersion) and reflections from impedance discontinuities, both of which lead to inter-symbol interference (ISI). Attempts to address these effects have employed various equalization schemes at the transmitter and receiver. Ideally, transmit and receive equalization work together to mitigate the degradation imposed by the channel, and thus allow increased data rates and/or reduced probability of communication errors.
In some systems, memory systems for example, the communicating ICs have an asymmetry to them that complicates optimization of the transmit and receive equalization schemes applied to counter the effects of the corresponding channel. For example, a memory controller that communicates with one or more memory devices may benefit from a fabrication technology that is different from that best suited for manufacturing the memory devices. It is therefore often the case that a memory controller can employ circuitry that exhibits significantly higher performance in speed and power than that of the associated memory device or devices. This process performance asymmetry between the communicating ICs complicates the task of optimizing equalization between the two types of devices.